Once we see that delay line lengths can be calculated using raster-scan numbers, we can see how the array behaves at its boundaries. Using Figure 2.9 as a guide, we see that PE 0's outputs are fed to PEs 4 and 5. Looking at the array further, we see that PE 3 must talk to PE 7 and 8. Thus the behavior of the left and right edges can now be understood, and is drawn in Figure 2.10. When data flows off the right hand side of the array, it essentially ``skips ahead'' one clock cycle. This provides interesting possibilities for time-domain multiplexing, and is discussed briefly in Chapter 5. However, for the most part these boundary conditions are not in the scope of this thesis.