List of Figures

• A sample 4x4 origami array.
• An origami array operating at full throughput and half throughput.
• An origami array after four and eight clock cycles running at half the maximum throughput rate.
• An origami array with half the number of processors, folded vertically.
• An origami array undergoing widthwise folding.
• A sample 4x4 alternate-slant architecture.
• The 4x4 alternate-slant architecture with the interconnection ``irregulaties'' abstracted away.
• A single-processor emulation of a 4x4 origami array using delay lines.
• The raster scan numbers for a 4x4 origami array.
• The interconnection of a 4x4 origami array including boundary conditions.
• The alternate-slant architecture.
• The module positions after placement.
• The final array after routing.
• The hand-optimized array after routing.
• The original four-bit ripple carry adder array, and the array after 3,750 optimization iterations.
• Iteration vs. cost for the four-bit ripple carry adder, starting temperature 1, temperature multiplier .99, 100 iterations.
• Iteration vs. cost for the four-bit ripple carry adder, starting temperature 10, temperature multiplier .99, 500 iterations.
• Iteration vs. cost for the four-bit ripple carry adder, starting temperature 25, temperature multiplier .99, 750 iterations.
• Iteration vs. cost for the four-bit ripple carry adder, starting temperature 40, temperature multiplier .99, 1,000 iterations.
• Iteration vs. cost for the four-bit ripple carry adder, starting temperature 55, temperature multiplier .996, 1,250 iterations.
• Iteration vs. cost for the four-bit ripple carry adder, starting temperature 70, temperature multiplier .999, 3,750 iterations.
• The ANDOR library routine.
• The four-bit ripple carry adder array.